High speed controlled rectifiers with deep level dopants



. /5 i Y L @Je M May 20, 1969- 5 T. J. DESMOND Y'x-:fr Al. 3,445,735

` HIGH SPEED CONTROLLED RECTIFIERS WITH DEEP LEVEL DOPANTS originalFiled nec. v, 1964 sheet of s IN VENTORS 77/#07//7 J. DESM/VD I-BYMWMMay 20, 1969 l l T vJ, ESMOND ET Al. 3,445,735

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United States Patent O ABSTRACT F THE DISCLOSURE A fast switchingsemiconductor device such as athyristor or controlled rectifiercomprising a crystalline semiconductive body having a PNPN structure,and a metaldiffused region adjacent one face of the body. The diffusedmetal is selected from the group consisting of nickel and cobalt.Adjacent the samegone face of the body having the metal-diffused regionis a zone diffused with a substance which reduces the lifetime ofminority charge carriers in that zone. The combination of the metal andthe substance prevents unduly increasing the resistivity of thesemiconductive body. When the semiconductive body consists of silicon,the lifetime killer is suitably gold.

This application is a division of application Ser. No. 416,521, filedDec. 7, 1964, issued Dec. 5, 1967 as U.S. Patent 3,356,543, and assignedto the assignee of this application.

BACKGROUND OF THE INVENTION Field of the invention This inventionrelates to improved semiconductor devices, and improved methods offabricating them.

Description of the prior art One class of semiconductive devicescomprises units having four zones or regions of alternate conductivitytypes, and three rectifying barriers 0r p-n junctions between the fourzones. For example, a device of this class may consist of a crystallinesemiconductive wafer having two opposing major faces; a P-type regionknown as the anode region adjacent one major wafer face; an N-typeregion known as the base region adjacent to the anode; a P-type regionknown as the gate region adjacent the base; an N-type region known asthe cathode region which extends from the gate region to the other majorwafer face; and separate electrical connections to the anode, gate, andcathode regions. Devices of this type are known as controlledrectiiiers, and are generally prepared from monocrystalline siliconwafers. They are also known as thyristors, and as PNPN or as NPNPswitches.

The switching speed of prior art controlled rectiers has not been asfast as is desirable for many applications. Attempts have been made toincrease the switching speed of controlled rectifers by diffusing intothe semiconductive body a substance which is a lifetime killer for theparticular semiconductor employed, that is, a substance which reducesthe lifetime of minority charge carriers in the semiconductor. Forexample, gold has been diffused into controlled rectifiers made ofsilicon in order to decrease the minority charge carrier lifetime of thedevices, and thereby increase their switching speed. However, when suchintroduction of a lifetime killer into a controlled rectifier isperformed by prior art methods 3,445,735 Patented May 20,` 1969 theresistivity of the semiconductive body is undesirably increased. Forexample, after the diffusion of gold into a silicon body, theresistivity of the semiconductive body in ohm-cm. is generally increasedby a factor of more than 2. This increase in resistivity degrades otherdesirable electrical device parameters, such as the voltage blockingcapability of the device for a given base width. If the base width isincreased to restore the voltage blocking capability, then the turn-offtime and the forward voltage drop of the device in the on state isundesirably increased.

Accordingly, it is an object of the invention to provide improvedsemiconductor devices.

Another object is to provide improved controlled rectifiers having highswitching speeds.

Still another object is to provide improved methods of fabricatingimproved semiconductor devices.

But another object is to provide improved methods of fabricatin-gimproved high speed controlled rectifiers.

The drawing The invention and its features will be described by thefollowing examples, considered in conjunction with the accompanyingdrawing, in which:

FIGURES la-lj are cross-sectional views of a semiconductive wafer duringsuccessive steps in the fabrication of one embodiment of a semiconductordevice;

FIGURES 2a-2b are cross-sectional views of a semiconductive wafer duringsuccessive steps in the fabrication of another embodiment of asemiconductor device; and

FIGURES 3a-3b are cross-sectional views of a semiconductive wafer duringsuccessive steps in the fabrication of another embodiment of asemiconductor device.

PREFERRED EMBODIMENTS Example I A body 10 (FIGURE la) of a crystallinesemiconductive material such as silicon, silicon-germanium alloys, andthe like is prepared with two opposing major faces 11 and 12. Theprecise size, shape, composition, conductivity type, and electricalresistivity of semiconductive body 10 is not critical. In this example,semiconductive body 10 consists of P conductivity type monocrystallinesilicon having a resistivity of about 20 to 40 ohmcm, and is in the formof a slice cut from a cylindrical ingot. Suitably, the slice is about 1"in diameter, and about 5 to 10 mils thick. In practice, a large numberof units are made simultaneously on the body 10. FIGURE l illustratesfor greater clarity the fabrication of only a single device from a smallpart of the entire semiconductive body or wafer 10. In FIGURES la-l j,the thicknesses of the various regions shown in the drawing are not toscale, having been exaggerated for greater clarity.

Zones of opposite conductivity type are now formed in semiconductivebody 10 immediately' adjacent each said major face. Such zones may bemade by standard techniques known to the semiconductor art, such asepitaxial deposition, or diffusion. In this example, epitaxial layers 13and 14 (FIGURE 1b) consisting of monocrystalline silicon of conductivitytype opposite to that of the original wafer are grown on wafer faces 11and 12 respectively. Since the original body 10 was P-type in thisexample, the epitaxial layers 13 and 14 consist of N-type silicon inthis example. Several techniques for the deposition of epitaxial layersof predetermined conductivityltype are described for example in RCAReview, vol. 24, No.` 4, p. 499-595, December 1963. The exact thicknessof epitaxial layers 13 and 14 is not critical, and is suitably about 1/zto 3 mils. Rectifying barriers 15 and 16 are formed at the interface orboundary between the original body 10 and the epitaxial layers 13 and 14respectively. In the following description, the term wafer will be usedto refer to the semiconductive body and the added epitaxial layers 13and 14 in any of the subsequent processing states.

Masking layers 17 and 18 (FIGURE 1c) are deposited on the surface ofepitaxial layers 13 and 14 respectively. Masking layers 17 and 18consist of an inert material which slows or prevents the difusion of aconductivity modifier into the semiconductivity modifier into thesemiconductive wafer. Suitable masking layers 17 and 18 may consist ofsilicon oxide, and may be deposited by heating the wafer in the vaporsof a siloxane compound, as described in U.S. Patent 3,089,793, issued toE. J. Jordan and D. I. Donahue on May 14, 1963, and assigned to theassignee of this application. Alternatively, when the semiconductivewafer consists of silicon, as in this example, the silicon oxide layers17 and 18 may be formed by heating the wafer for several hours in anambient containing oxygen, or water vapor, or both.

A predetermined ring-shaped or annular portion of one silicon oxidelayer 17 is removed from the suface of epitaxial layer 13 by anconvenient method, such as lapping, or grinding, or masking and etching.An annular portion 19 (FIGURE 1d) of epitaxial layer 13 is thus exposed.The wafer is now heated in the vapors of a conductivity modier capableof inducing in the semiconductive layer 13 the conductivity type of theoriginal body 10. In this example, since body 10 consists of P-typesilicon, the wafer is heated in the vapors of an acceptor such as boronoxide (B203) or the like. Boron is thereby diffused into the exposedportion of epiltaxial layer 13, while the silicon oxide layer 18 and theremainder of silicon oxide layer 17 serve as masks against the diffusionof boron into the unexposed portion of the wafer. A thin annular orring-shaped boron-diffused P-type region is thus formed in layer 13immediately adjacent the exposed surface portion 19 thereof. Theboron-diffused region 20 is thinner than the N-type epitaxial region 13.A rectifying barrier or p-n junction 21 is thus formed at the boundaryor interface between boron-diffused P-type region 20 and the remainderof the N-type epitaxial layer 13.

The masking layers 17 and 18 are now removed. When layers 17 and 18consist of silicon oxide, as in this example, they are convenientlyremoved by treating the wafer with an aqueous hydrouoric acid solution.Thin metallic films 22 and 23 (FIGURE 1e) are now deposited on thesurfaces of epitaxial layers 13 and 14 respectively by any convenientmethod. Metallic lms 22 and 23 may suitably consist of nickel, cobalt,or alloys of these, and may be deposited, eg., by evaporating, orsputtering, or electroplating, or electroless plating. In this example,metallic layers 22 and 23 consist of cobalt, are about 0.01 to 0.5 milsthick, and are deposited by electroless plating techniques, such asdescribed in U.S. Patent 2,430,581, issued Nov. 11, 1947, to L. Pessel,and assigned to `the assigness of this application.

The semiconductive body of Wafer 10 is now heated in a non-oxidizingambient for about 1A; to 1 hour at a temperature of about 850 C. Theambient may be an inert gas such as argon, nitrogen, and the like, or areducing gas such as forming gas, hydrogen, and the like. During thisstep, the metallic lms 22 and 23 are sintered and diffused into thesemiconductive body 10, and appear to act as getters by serving as asink into which some of the impurities present in the semiconductivebody 10 and epitaxial layers 13 and 14 can diffuse. The semiconductivebody 10 is now treated in a boiling solution of a metallic chloride suchas zinc chloride or nickel cholride in hydrochloric acid for a period oftime sufficient to remove all of the excess metal from the surfaces ofthe semiconductive wafer. A period of about 1 to 30 minutes is usuallysufficient for this purpose. This treatment removes all of the excessmetal of layers 22 and 23 which has not been diffused into the wafer 10and the layers 13 and 14. Adjacent the surface of epitaxial layers 13and 14, two cobalt-diffused regions 24 and 25 respectively (FIGURE 1f)are thus formed. The cobalt-diffused regions 24 extends across theboron-diffused regions 20 as well as -the remainder of the epitaxiallayer 13.

Advantageously, wafer 10 is now treated in a hydrofluoric acid solutionto remove any oxides which may have formed on the Wafer surface.

A thin film (FIGURE 1g) of a substance which is a lifetime killer forthe semiconductive body 10 is now deposited on the surface of epitaxiallayer 14 by any convenient method. In this example, wherein thesemiconductive body 10 consists of silicon, the film 30 of lifetimekilling material suitably consists of gold, and is convenientlydeposited by evaporation. Preferably, lm 30 is not less than l and notmore than 200 angstroms thick.

The semiconductive wafer is now heated in a nonoxidizing ambient forabout 1A to 5 hours. It has been found that for best results, that is,for minimum increase of wafer resistivity, the temperature of thisheating step should be maintained within narrow limits of about 860 C.to 900 C. At lower temperatures, not enough gold diffuses into thewafer, while at higher temperatures the resistivity of the waferincreases rapidly and undesirably. During this step, the gold film 30diffuses through the metal-diffused region 25 and into the siliconWafer. The gold-diffused region (FIGURE lh) thus formed is thicker thanthe metal-diffused region 25, and extends through the thickness of layer14 at least to p-n junction 16, and preferably to p-n junctions 15 and21. Conveniently, this ditfusion step is performed for a period of timesufficient to diffuse the lifetime killer (gold in this example) throughthe entire thickness of the semiconductive wafer.

The semiconductive wafer is now cooled to room temperature. For bestresults and minimum increase in Wafer resistivity the cooling rateshould not exceed 200 C. per minute. It is preferred to cool thesemiconductive wafer at a much slower cooling rate of about 1 to 10 C.per minute.

The surface of epitaxial layer 13 is now suitably masked by anyconvenient method, for example by means of a photoresist layer (notshown). A metallic electrode layer 33 (FIGURE 1h) is deposited on theentire surface of epitaxial layer 14 by any convenient method. Ametallic electrode 31 is deposited on a portion of epitaxial layer 13,and an annular or ring-shaped metallic electrode 32 is deposited onepitaxial layer 13 around electrode 31 and in contact with the annularP-type region 20. Conveniently, the electrodes 31, 32 and 33 consist ofthe same metal or alloys, and are deposited simultaneously. In thisexample, the electrodes 31, 32 and 33 consist of nickel, and aredeposited by standard electroplating techniques. The electrodes 31, 32and 33 may subsequently be given a coating (not shown) of a metal suchas lead to facilitate the bonding of electrical lead wires thereto.

The semiconductive wafer is now diced into individual pellets or dies(FIGURE 1j), each die being about 50 mils square in this example. Themetallic layer 33 of each individual die 40 is bonded to a metallicheader 45. Electrical lead wires 41 and 42 are attached to electrodes 31and 32 respectively, for example by thermocompression bonding. In theoperation of the device, the header serves as the anode lead, lead wire41 serves as the cathode lead and lead wire 42 serves as the gate lead.

The conductivity types of the various regions in the device of thisexample may be reversed, using suitable acceptors and donors for each.

It has unexpectedly been found that when a lifetime killer such as goldis introduced into a semiconductive wafer lby diffusion at a particulartemperature range through a wafer surface zone which has previously beendiffused with a metal such as nickel or cobalt, the increase in waferresistivity is minimized. Additional improvement is obtained if thewafer is then cooled to room temperature at a rate less than 200 C. perminute. The increase in resistivity of the Wafer is then generally lessthan 100 percent. Moreover, the electrical parameters of the completeddevice, such as the blocking capa- Ibility, are unexpectedly improved.The reasons for this improvement are not presently clear, but theinvention may be practiced without regard to Whatever theory is selectedto explain the observed results.

Example II In the previous example, the semiconductive -body utilizedconsisted of P-type silicon, and epitaxial techniques were employed. Inthis example, a P-type semiconductive body and diffusion techniques areemployed.

Referring now to FIGURE 2a, a semiconductive body having two opposingmajor faces 11' and 12 is prepared. In this example, thesemiconductivebody 10 consists of a monocrystalline P-type silicon-germanium alloy,such as is described in B. Selikson U.S. Patent 2,997,410, issued onAug, 22, 1961, and assigned to the assignee of this application. Asilicon-rich alloyis preferred for this purpose.

Semiconductive body 10' is heated in the vapors of a conductivitymodifier capable of inducing opposite conductivity type in thesemiconductive body. In this example, since the semiconductive body isP-type, a suitable conductivity modifier is a donor such as arsenic orphosphorus. The semiconductive body 10' is heated in the vapors ofphosphorus pentoxide for about 10 hours at about 1250 C. to form twophosphorus-diffused N-type zones 13 and 14 (FIGURE 2b) adjacent majorwafer faces 11 and 12 respectively. Zones 13' and 14 are suitably about1/2 to 3 mils thick. Rectifying barriers 15' and 16' are formed betweenthe N-type diffused regions 13' and 14 respectively, and the P-type bulkof semiconductive body 10. It will be recognized that the generalconfiguration of semiconductive Wafer in FIGURE 2b is now similar tothat of the semiconductive wafer in FIG- URE lb, except that theconductivity types of the various zones are reversed. The wafer ofFIGURE 2b has a PNP structure, while the wafer of FIGURE 1b has an NPNstructure. The remaining steps of this embodiment will be described withreference to FIGURES lc-1j.

Masking layers 17 and 18 (FIGURE 1c) are now deposited on Wafer faces 11and 12 respectively. If the masking layers cannot be made by thermaloxidation of the wafer, other masking materials such as magnesium oxidemay be utilized. Alternatively, an organic siloxane compound may Ibethermally decomposed, and the decomposition products forced through ajet to impinge upon the semiconductive wafer and thus coat the Waferwith silicon oxide, as described in I. Klerer U.S. Patent 3,114,663,issued Dec. 17, 1963, and assigned to the assignee of this application.

The fabrication of the device is continued in a manner similar to thatdescribed in Example I above. An annular portion of masking layer 17 isremoved, exposing an `annular portion 19 (FIGURE 1d) of N-type zone 13.An acceptor lsuch as boron or the like is now diffused into the unmaskedportion of wafer 10 to form a P-type region 20 within the N-type zone13, and a p-n junction 21 between the boron-diffused region 20 and thephosphorus-diffused zone 13.

Masking layers 17 and 1.8 are now removed, and metallic layers 22 and 23(FIGURE le) are deposited on the surfaces of zones 13 and 14respectively. In this example, the metallic films 22 and 23'4 consist ofan alloy of nickel and cobalt. The alloy may be conveniently depositedby the electroless plating method mentioned above. The semiconductivebody 10 is then heated to sinter the metallic films 22 and 23. Portionsof metallic films 22 and 23 diffuse into zones 13 and 14 respectively,forming the metal-diffused zones 24 and 25 (FIGURE lf) respectively. Theremaining portions of the sintered metallic films 22 and 23 are nowremoved by any convenient method, for example by treating the wafer in ahot aqueous solution of nickel chloride, cobalt chloride, andhydrochloric acid.

A gold film 30 (FIGURE lg) about l to 200 angstroms ,thick is depositedon the surface of zone 14. The 'wafer 10 is then heated in anon-oxidizing ambient to a temperature of about 860 C. to 900 C. so asto diffuse the gold film 30 into the Wafer, and form a gold-diffused'region 35 therein. Wafer 10 is then cooled to room temperature at arate less than 200 C. per minute.

The remaining steps of forming electrodes 31, 32 and 33 (FIGURE 1h) tozone 13, region 20 and zone 14 respectively, dicing the wafer into dies,mounting each die 40 on a header 45 (FIGURE lj) and attaching electricallead wires 41 and 42 to electrodes 31 and 32 respectively, are performedby standard methods of the art as described in Example I.

Example III In this example, a semiconductive body 10" (FIGURE 3a)consisting of N conductivity type monocrystalline silicon having aresistivity of about 20 to 40 ohm-cm. is prepared as ya Wafer With twoopposing major faces 11" and 12". Suitably, wafer 10 is about 5 to 10mils thick.

Referring now to FIGURE 3b, the semiconductive body 10" is heated in anambient including the vapors of an acceptor such as boron and the liketo form two borondiffused P-type zones 131" and 14 immediately adjacentwafer faces 11" and 12 respectively. In this example, body 10 is heatedin an ambient of nitrogen and boron oxide (B203) vapors for about 20hours at about 1300 C. A suitable ambient concentration of boron oxidevapors may be obtained by heating a container of boron oxide (not shown)to about 860 C. The P-type boron-diffused zones 13" and 14" thus formedabout 1% to 2 mils thick, and the concentration of boron atoms on waferfaces 11" and 12" is about 2 1018 per cm. The general configuration ofthe semiconductive wafer in FIGURE 3b is now similar to that 'of thewafer in FIGURE lb. The remaining steps of this embodiment will bedescribed with reference to FIGURES lc-lj.

Wafer 10 is now heated in steam for about 3 hours at about l200 C.Silicon oxide layers 17 and 18 (FIGURE 1c) `are thus formed on thesurfaces of the boron-diffused zones 13 and 14 respectively. An annularportion of silicon oxide layer 17 is removed by standard masking andetching techniques, thus exposing the corresponding portion (FIGURE 1d)of boron-diffused zone 13. Wafer 10 is reheated in the vapors ofphosphorus pentoxide for about 11/2 hours at about l225 C. to form aphosphorusdiffused N-type region 20 within the boron-diffused zone 13. Ap-n junction 21 is formed at the interface between N-type region 20 andP-type zone 13.

Silicon oxide layers 17 and 1-8 are removed by treating the wafer in anaqueous solution of hydrofluoric acid. Nickel films 22 and 23 aredeposited on the surface of zones 13 and 14 by standard electroplatingtechniques, such as described in A. Brenner, Electrodeposition ofAlloys, Academic Press, New York, 1963. The silicon body 10 is thenheated in a moist hydrogen ambient at about '850 C. to sinter the nickelfilms 22 and 23. A portion of the nickel diffuses from films 22 and 23into wafer zones 13 and 14 respectively, forming nickeldiffused regions24 and 25 (FIGURE lf) respectively.

Wafer 10 is treated in a boiling solution of nickel chloride andhydrochloric acid for a period of about 1 to 30 minutes to remove thesintered nickel films 22 and 23. A gold film 30` (FIGURE lg) about l to200 angstroms thick is deposited on the surface of zone 14. The wafer isthen heated in a nonoxidizing ambient for about 1A to 5 hours at about860 C. to 900 C. The gold film 30 is thus diffused into the wafer,forming a gold-diffused region C. per minute. It has unexpectedly beenfound that the o restivity of the silicon wafer is not increased at allif gold is diffused into the wafer in the manner described.

The remaining steps of attaching electrodes to the diffused region 21and to zones 13 and 14, then ydicing the wafer into dies, mounting eachdie on ya metallic header, and attaching electrical lead wires to theelectrodes, are similar to those described in Example I above.

Prior art silicon controlled rectifiers have a turn-off time of about 20to 40 microseconds. llt has been found that silicon controlledrectifiers made as described in this example have a turn-'off time ofabout 2 to 5 microseconds, which is an improvement of about an order ofmagnitude.

It has also been found that the blocking capability of the controlledrectifiers fabricated according to the invention is unexpectedlyimproved. Conventional silicon controlled rectifiers of the prior arthave a blocking capaccontrloled rectifiers of the prior art have ablocking capability of about 800 volts, whereas devices according tothis example have a blocking capability of about 1000 volts.

While the invention has been described above in terms of a controlledrectifier, the same technique for decreasing the minority carrierlifetime of a semiconductive body without unduly increasing theresistivity of the lbody may be applied to the fabrication of othersemiconductive devices such as transistors and rectifiers.

It will be understood that the above examples are by way of illustrationonly, and not limitation. Other semiconductive materials may beutilized, together with appropriate lifetime killers and acceptors anddonors. The invention may also be practiced by diffusing the nickel orcobalt into only one major wafer face, and subsequently diffusing thelifetime killer into the wafer through the same one wafer face. Variousother modifications may be made by those skilled in the art withoutdeparting from the spirit and scope of the invention as set forth in thespecification and appended claims.

We claim:

1. A semiconductive device comprising a crystalline semiconductive bodyof given conductivity type having first and second opposing faces:

first and second zones of opposite conductivity type adjacent said firstand second faces respectively;

rectifying barriers between said first and second zones and said body;

a region of said given conductivity type in said first zone immediatelyadjacent said first face;

a rectifying barrier between said region and said first zone;

a metal-diffused region immediately adjacent said second face, saidmetal being selected from the group consisting of nickel, cobalt, andnickel-cobalt alloys;

a third zone adjacent said second face containing a substance whichreduces the lifetime of minority charge carriers in said body, saidsubstance being different from said metal; and

electrical connections to said first and second zones and to said giventype region.

2. A device as in claim I, wherein said substance in said third zone isgold.

3. A semiconductive device comprising a crystalline semiconductive bodyof given conductivity type having first and second opposing faces;

first and second epitaxial layers of opposite conductivity typesemiconductive material adjacent said first and second facesrespectively;

rectifying barriers between said first and second epitaXial layers andthe bulk of said body;

a region of said given conductivity type in said first epitaxial layerimmediately adjacent the surface of said first layer;

a rectifying barrier between said given conductivity type region and thebulk of said first epitaxial layer;

a metal-diffused region immediately adjacent the surface of said secondepitaxial layer, said metal being selected from the group consisting ofnickel, cobalt, and nickel-cobalt alloys;

a third zone adjacent the surface of said second epitaxial layercontaining a substance which reduces the lifetime of minority chargecarriers in said body, said substance being different from said metal;and

electrical connections to said first and second epitaxial layers and tosaid given type region.

4. A semiconductive device comprising a monocrystalline silicon body ofgiven conductivity type having first and second opposing faces;

first and second zones of opposite conductivity type adjacent said firstand second faces respectively;

first and second rectifying barriers between said first and second zonesand the bulk of said body;

a region of said given conductivity type in said first zone immediatelyadjacent said first face;

a third rectifying barrier between said region and said first zone;

a nickel-diffused region immediately adjacent said second face;

a third zone immediately adjacent said second face diffused with gold,said gold-diffused zone being thicker than said nickel-diffused region;and

electrical connections to said first and second zones and to said givenconductivity type region.

References Cited UNITED STATES PATENTS 3,246,172 4/1966` Sanford 307-8853,327,183 6/1967 Greenberg et al. 317-235 3,342,651 9/1967 Raithel148-188 3,349,299 10/ 1967 Herlet 317-235 JOHN W. HUCKERT, PrimaryExaminer.

R. F. SANDLER, Assistant Examiner.

U.S. Cl. X.R. 14S-175, 1818

